There is a continuing trend within the microelectronics industry to incorporate more circuitry having greater complexity on a single integrated circuit (IC) chip. Maintaining this trend generally entails shrinking the size of individual devices within the circuit by reducing the critical dimensions (CDs) of device elements along with the pitch, or the CD of such an element added to the spacing between elements. Microlithography tooling and processing techniques play an important role in resolving the features necessary to fabricate devices and accordingly, are continually under development to meet industry milestones relating to the CD and pitch characteristic of each new technology generation.
High numerical aperture (NA) projection stepper/scanner systems in combination with advanced photoresist processes now are capable of routinely resolving complex patterns that include isolated and dense resist features having CDs and pitches, respectively, well below the exposure wavelength. However, to meet the requirements of device design rules which continue to push the resolution limits of existing processes and tooling, other more specialized techniques have been developed to further enhance resolution. These include double patterning technology (DPT) techniques in which device patterns having potentially optically unresolvable features are decomposed into two or more complementary, and more easily resolvable patterns, each containing features with larger CDs and/or a relaxed pitch.
For traditional layout designs, multiple layout topologies exist per functionality. For DPT-compliant layout designs, in addition to multiple layout topologies, multiple DPT-compliant solutions exist per layout topology. Thus, two needs arise. First, DPT-compliant layouts generated for alternative layout topologies need to be systematically, automatically, and quickly evaluated for robustness to process variability. Secondly, guidance is needed for modifying DPT-compliant layouts such that their robustness to process variation can be opportunistically improved.
FIG. 1 depicts two exemplary DPT layouts (layouts “1” and “2”), which are intended to result in the same IC. Part 150 of FIG. 1 presents the original drawn layout and two alternative DPT-compliant solutions. Part 160 of FIG. 1 presents the corresponding printability simulations and shows that the DPT-compliant solution on the left (solution “1”) is better than the one on the right (solution “2”), because solution “2” is vulnerable to pinches. A pinch, marked in FIG. 1 by the “X”, is a point on the fabricated IC chip that is narrower than set forth in the design layout. The lack of an evaluation methodology can be a significant handicap when comparing the performance of alternative DPT-compliant solutions and competing decomposition algorithms.
Currently, the quality of DPT-compliant layouts is judged based on a binary pass/fail check, which provides a basic but incomplete evaluation. The decomposition algorithms are evaluated indirectly by comparing the results for a limited set of benchmark circuits. Since simulations are slow and computationally-expensive, a rule-based methodology is needed to systematically evaluate alternative DPT-compliant layout solutions such that guidance can be provided for layout optimizations.